The present invention relates to the field of interconnect structures for integrated circuit packages, and in particular, to a copper interconnect structure for electrically connecting two or more electronic components.
Chip interconnection in the semiconductor processing industry often employs two steps. First, in chip bonding, the back of a chip is mechanically attached to an appropriate medium such as a ceramic substrate or a paddle of a metal lead frame. Next, the bond pads on the circuit side of the chip are electrically connected to the package leads by a wire or other electrical conductors to permit utilization of the integrated circuit (IC). Common methods for connecting the bond pads to the leads of lead frame, or the conductors of other conductor support devices, are by wire bonding, Tape Automated Bonding (TAB), Controlled Collapse Chip Connection (C4) or bump bonding, and through the use of conductive adhesives.
Aluminum bond pads are commonly employed on IC dies, but a significant problem with their use is the rapid formation of a tenacious nonconductive oxide on the surface of the metal, even at room temperature. When an interconnect is made to the bond pad, the nonconductive oxide causes the interconnect to have high contact resistance. The resistance typically ranges from hundreds to millions of ohms.
In an effort to reduce the contact resistance, a noble metal, such as gold, has been used to provide an inert, oxide-free surface on the bond pad. The presence of gold on the bond pad precludes the formation of nonconductive metal oxides at the surface of the contact. Nevertheless, the gold plating of the bond pads of a semiconductor die is an elaborate process that can be very difficult, expensive and time consuming.
Efforts have been aimed at refining the understanding of the oxidation mechanisms in metals employed in the bond pads. Recently, studies have been done on copper and copper oxide, mainly because copper has become a promising interconnect material for the next generation of integrated circuits because of high conductivity and good resistance to electromigration.
For example, W. A. Lanford studied ion implantation as an effective way to passivate copper films. Lanford, W. A. et al., Low-temperature passivation of copper by doping with Al or Mg, in THIN SOLID FILMS, 234-41 (1995). By analyzing the growth mechanism for copper, Lanford observed that the oxidation rate could be reduced by adding only a very small concentration of dopant, such as Al or Mg, to the copper.
Similarly, the corrosion resistance of boron (B) implanted copper, particularly its mechanism, has been studied by P. J. Ding et al. in Investigation of the mechanism responsible for the corrosion resistance of B implanted copper, B 85 NUCL. INSTRUM. METHODS PHYS. RES., 260-63 (1994). By investigating the oxidation of boron implanted copper and copper oxide (Cu2O), Ding found that the oxidation rate of Cu2O implanted with boron is as low as that of copper metal (Cu) implanted with boron. Moreover, Ding reported that, on boron implanted copper, it is the CuO that forms, and not the Cu2O that typically forms on a non-implanted copper.
Other methods of solving the oxide problem have involved scraping the bond pad to remove oxide immediately before the interconnect is formed, or using a barrier layer on the bond pad. For example, U.S. Pat. No. 4,987,750 describes the use of titanium nitride (TiN), tungsten (W), tungsten nitride (WN), zirconium nitride (ZrN), titanium carbide (TiC), tungsten carbide (WC), tantalum (Ta), tantalum nitride (TaN), or titanium tungsten (TiW) as barrier layers for copper. Many of these materials, however, also form nonconductive oxides, or have poor electrical or thermal conductivity, or a high thermal expansion.
Further, many of these barrier layers exhibit instability at temperatures higher than 400xc2x0 C. Since a silicon substrate is generally subjected to subsequent steps during the IC fabrication, such as annealing or reflow processes which require temperatures higher than 400xc2x0 C., there is a need for a barrier layer that is stable at the high temperatures required for subsequent substrate processes steps. Also, since copper is increasingly used in the electrical interconnection technology, it is desirable to further improve the processes in which copper oxidation is effectively prevented, while its metallization resistance is kept low even after the substrate has undergone subsequent processing steps.
Accordingly, there is a need for an improved bond pad structure of an integrated circuit die that would not oxidize to form a nonconductive material. A copper bond pad with a suppressed oxide growth layer having good electrical conductivity, good thermal conductivity, and low thermal expansion is also needed, as well as a simple process for forming such copper bond pads.
The present invention provides an interconnect structure comprising a multi layered copper bond pad on the surface of a semiconductor die. The outermost exposed surface of the bond pad is a titanium implanted layer that protects the underlying conductive copper layer from oxidation due to exposure to ambient environmental conditions, which can lead to bonding failure, by suppressing the copper oxide growth in the bond pad. An electrical interconnect structure such as a wire or solder ball bump may be placed directly on the implanted copper layer in order to connect the copper bond pad to a lead frame or other conductive structure.
The present invention also provides for the passivation of copper surfaces by employing a Ti/Al barrier layer on the copper bond pad that enhances the bonding yield by increasing the contact adhesion between the metal layer and the bonding structure.
These and other advantages and features of the invention will be more clearly understood from the following detailed description of the invention which is provided in connection with the accompanying drawings.